A static random access memory (SRAM) is known as a kind of semiconductor memory devices. To increase the operating speed of the SRAM, it is possible to reduce a bit line delay. The bit line delay is the time from the opening of a word line to the appearance of a signal having a desired amplitude on a bit line. The magnitude of the amplitude is determined by the offset voltage of a sense amplifier for amplifying the signal on the bit line. A signal amplitude exceeding the offset voltage of the sense amplifier is unnecessary for sensing, and increases the power consumption.
Decreasing the power supply voltage is generally an effective means for implementing a low-power-consumption operation, but it is not always possible to sufficiently achieve the effectiveness for the SRAM. This is so because the power of the SRAM is mainly consumed by the charge/discharge of bit lines, and the power consumption by the charge/discharge of bit lines is proportional to the bit line amplitude that is determined by the offset voltage of the sense amplifier and almost independent of the power supply voltage. Therefore, while the power consumption reduces in proportion to the second power of the power supply voltage in a normal logic circuit, the power consumption can be reduced in proportion to only the first power of the power supply voltage in the SRAM.
In addition, when the SRAM is operated at a low voltage, the variation in cell current increases. Accordingly, if sense amplifier activation and word line deactivation are performed in accordance with a cell having the lowest operating speed in a memory cell array, a signal larger than an amplitude necessary for sensing appears on a bit line for a cell other than the slowest cell, and the power is consumed more than necessary.